Automated universal array

ABSTRACT

A large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing. Interconnection and vertical signal routing between cell rows can be made through a feedthrough in each internal cell and connection to selective vertical tunnels without touching the overhead horizontal wiring channels which provide horizontal signal routing. A side peripheral roadbed area adjoins the cell rows and inner roadbed area and consists of an alternating pattern of horizontal and vertical tunnels which permit interfacing with a bordering arrangement of peripheral cells consisting of basic peripheral cells and special purpose cells as well as providing coupling to a pair of common power busses which are located on the outer perimeter of the array.

This application is a continuation of application Ser. No. 305,825,filed Sept. 28, 1981, now abandoned.

This invention relates generally to large scale integrated arrays ofsemiconductor devices and more particularly to a universal array ofCMOS/SOS logic gates.

BACKGROUND OF THE INVENTION

Large scale integrated arrays of standard cells interconnected invarious configurations are well known. Universal arrays of logic gatesare also known and consist of a fixed placement of semiconductor logicdevices and tunnels arranged in a repetitive ordered structure on asubstrate typically silicon or sapphire. All device nodes (gates,drains, sources and tunnel ends) are accessible and by means of ametallization mask, a predetermined metallization pattern ofinterconnects is laid down for implementing a particular circuitconfiguration. Typical examples of this type of technology are shown anddescribed in th following patents: (a) U.S. Pat. No. 3,365,707,entitled, "LSI Array and Standard Cells", issued Thomas R. Mayhew onJan. 23, 1968; (b) U.S. Pat. No. 3,638,202, entitled, "Access CircuitArrangement for Equalized Loading in Integrated Circuit Arrays", issuedto Paul R. Schroeder on Jan. 25, 1972; and (c) U.S. Pat. No. 4,161,662,entitled, "Standardized Digital Logic Chip", issued to Robert B.Malcolm, et al on July 17, 1979.

While the various arrangements as shown and described in thesereferences all have one thing in common, that is, an orderly uniformarrangement of standard logic cells with intermediate cross-over andcross-under power and data interconnects, they do not lend themselves toautomatic layout techniques. This is due to the fact that the relativeinaccessibility of the basic internal cells and the adjoining roadbedinterconnect routing area do not lend themselves to an optimization ofmetal routing on a single level for interconnecting the devices in aparticular logic configuration as desired by the circuit designer.

It is an object of the present invention, therefore, to provide animprovement in large scale integrated arrays fabricated on asemiconductor substrate.

It is a further object of the present invention to provide a universalarray of uncommitted semiconductor devices having optimum pinaccessibility.

Still a further object of the present invention is to provide anautomatic universal array particularly adapted for automated layouttechniques which is adapted to implement a single level of interconnectsto a plurality of logic gates by an optimum routing pattern.

SUMMARY

These and other objects are achieved by means of a large scaleintegrated universal array designed for single level metal routing andcompatibility with automatic layout techniques and comprises a layouthaving a generally rectangular inner region of uncommitted identicalbasic internal cells arranged in parallel horizontal rows separated by aplurality of, at least three, mutually separated vertical tunnelpatterns of plural tunnel sets defining an inner roadbed area for makingstraight line or diagonal interconnects vertically between adjacent cellrows. An outer border of peripheral cells are located adjacent the cellrows with an intermediate side peripheral roadbed area consisting ofalternating horizontal and vertical tunnel patterns being provided formaking interconnects to the peripheral cells and coupling outlyingbordering power busses to the internal cells. The vertical andhorizontal tunnel patterns, moreover, define areas over which aplurality of spaced apart horizontal and vertical interconnect wiringchannels, respectively, can be formed for facilitating horizontal andvertical signal routing. Each basic internal cell comprises asymmetrical four transistor logic gate having a two input gate functionfor providing a dual entry vertically on each side of the cell. Eachbasic cell additionally has a feedthrough capability permitting signalsto pass through a particular cell row. The inner roadbed area in itspreferred form consists of five tunnel patterns between cell rowspermitting fifteen horizontal metal interconnect wiring channels, ingroups of three, to be implemented between cell rows. The borderingperipheral cells are of a well known conventional design and comprisebasic peripheral cells that can be used to interface off-chip andspecial peripheral cells which include high impedance devices, lowimpedance devices, diodes and special custom circuits

The foregoing as well as other objects, features and advantages of theinvention will become apparent from the following detailed descriptionwhen taken in conjunction with the appended drawings which areidentified as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view generally illustrative of the layout of theautomatic universal array which comprises the subject invention;

FIG. 2 is an enlarged sectional view of a portion of the layout shown inFIG. 1;

FIG. 3 is a diagram illustrative of the layout of the vertical andhorizontal tunnel patterns in the inner and peripheral roadbed areas ofthe subject invention;

FIG. 4 is a diagram illustrative of the layout of one basic internalcell and the adjoining vertical tunnel pattern on either side thereof;

FIG. 5 is a diagram of the layout of a basic internal cellinterconnected to function as a two input NAND gate; and

FIGS. 6A and 6B are a generalized layout and diagram of the componentparts of a basic peripheral cell utilized in the subject invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings wherein like numerals refer to likecomponents throughout, reference is first made to FIGS. 1 and 2 whereinthere is shown a layout and section therefrom generally illustrative ofa universal array in accordance with the subject invention which, in itsbasic form, is comprised of: (a) a plurality (ten) of horizontal rows10₁, 10₂ . . . 10₁₀ of identical contiguous basic internal cells 12 ofwhich there are, for example, 64 per row; (b) an inner roadbed area (13)consisting of nine intermediate vertical polysilicon tunnel patterns14₁, 14₂ . . . 14₉ between cell rows as well as an outer roadbed area13' consisting of top and bottom end vertical polysilicon tunnelpatterns 16₁ and 16₂ adjoining the first and last rows 10₁ and 10₁₀ ;(c) a bordering configuration of peripheral cells including basic andspecial peripheral cells 18; and (d) a side peripheral roadbed area 21located at the right and left sides of the array providing an interfacebetween the cell rows and peripheral cells and consisting of horizontalpolysilicon tunnel patterns 22₁, 22₂ . . . 22₁₁, respectively locatedadjacent the vertical tunnel patterns 16₁, 14₁ . . . 14₉, and 16₂, andwith alternate relatively smaller polysilicon vertical tunnel patterns24₁, 24₂ . . . 24₁₀ located adjacent the ends of the respective cellrows 10₁, 10₂ . . . 10₁₀.

The elements, moreover, are fabricated in the form of a chip 25utilizing silicon on sapphire (SOS) techniques. A repetitive portion ofthe array shown in FIG. 1 is shown in greater detail in FIG. 2.Referring now to FIG. 2, the row 10₁ of basic internal cells, forexample, is located between the outer and top vertical tunnel pattern16₁ and the first inner vertical tunnel pattern 14₁ which isintermediate the cell row 10₁ and cell row 10₂. As shown, the tunnelpattern 14₁ and the other tunnel patterns 14₂ . . . 14₉ between cellrows consist of five sets of tunnels each while the outer verticaltunnel pattern 16₁ is comprised of three sets of tunnels. Moreparticularly, the tunnel pattern 14₁ is comprised of five like numberedsets of equal length parallel tunnels 14₁ -1, 14₁ -2 . . . 14₁ -5 whichare linearly arranged with one another and spaced equidistantly apartfrom one another. Likewise, the outer vertical tunnel pattern 16₁ iscomprised of three sets of tunnels 16₁ -1, 16₁ -2 and 16₁ -3.

As will become evident, the vertical tunnel patterns in the inner andouter roadbed areas 13 and 13' provide a number of discrete polysilicontunnels which are adapted to encompass all available vertical wiringchannels possible in the array while the horizontal tunnel patterns 22₁,22₂, etc. in the side peripheral roadbed area 21 are adapted toencompass substantially all available horizontal wiring channels andinterconnects between the internal rows of basic cells 12 and theperipheral cells 18. Additionally, the sets of alternating verticaltunnels 24₁, 24₂, etc in line with the horizontal tunnel patterns 22₁,22₂, etc in the peripheral roadbed area provide cross-unders for pluralvertical wiring channels and interconnects between the horizontal tunnelpatterns 22₁, 22₂ allowing a power bus, for example the busses 28₁, 28₂,etc. to be coupled thereacross to the cell rows 10₁, 10₂, etc. The powerbusses 28₁, 28₂, etc., as shown in FIG. 2, connect to first verticalpower bus 30 which connects to a bonding pad 34 in the corner of thearray which is adapted to have, for example, a +V power potentialapplied thereto from off-chip. Immediately adjacent the bonding pad 34is a second bonding pad 36 which is adapted to be connected to theopposite polarity power supply potential -V. The bonding pad 36 isconnected to a second vertical power bus 38 which runs parallel to thepower bus 30. Both power busses 30 and 38 are repeated on the other sideof the array and run through the vertically aligned peripheral cells 18.The bonding pad 34 also connects to a first horizontal power bus 40while the bonding pad 36 connects to a second horizontal power bus 42 bymeans of a bridge 44 over the power bus 30 and intermediate power bussegments 46, 48 and 50. As shown in FIG. 1, the same configuration isprovided at the opposite diagonal corner of the array. Thus, both +V and-V power busses encircle the outer periphery of the array serving notonly to power the peripheral cells 18 but also the internal cells 12 ofthe basic internal cell rows 10₁, 10₂ . . . 10₁₀.

The inter-relationship between one inner vertical tunnel pattern e.g.tunnel pattern 14₁ and its neighboring peripheral horizontal andvertical tunnel patterns 22₂ and 24₁ is further illustrated in FIG. 3.There the five sets of inner roadbed tunnels 14₁ -1. 14₁ -2, 14₁ -3, 14₁-4 and 14₁ -5 between cell rows 10₁ and 10₂ are shown consisting of aplurality of identical polysilicon tunnels 52 which terminate inexternally accessible metal contact pads or pins 54 and 56 at each endthereof. The upper contact pins 54 of the tunnel pattern 14₁ -1 arelocated immediately adjacent the lower side of cell row 10₁ while theupper side thereof is adjacent the lower contact pins 56 of the outerroadbed tunnel pattern 16₁ -3. The significance of this arrangement willbecome apparent when FIG. 4 is considered.

With respect to the lower pins 56 of tunnel pattern 14₁ -1, they arespaced apart from a like number of upper contact pins 54 of the nexttunnel pattern 14₁ -2. This vertical arrangement of spaced apart contactpins proceeds to a like number of contact pins 56 of the fifth tunnelpattern 14₁ -5 which is immediately adjacent cell row 10₂. Thus,metallization contacts can be made from cell row to cell row through thetunnel vertical patterns by any number of vertical interconnects 62,diagonal interconnects 64, or horizontal metal channels 66, as shown.

The tunnel length of all the tunnels 52 of all the vertical tunnelpatterns in the inner and outer roadbed areas 13 and 13' have a lengthof a predetermined vertical dimension so that one, two or threehorizontal metal channels 66₁, 66₂ and 66₃ can be over-laid as desired.These horizontal metal channels are adapted to primarily connect toselective vertical tunnel pins 54 or 56 for providing the desired logicrouting within the array and accordingly to contact pins 68 of theoutlying tunnels 70 of the horizontal tunnel pattern 22₂. The horizontaltunnels 70 are repeated fifteen times in order to accommodate threehorizontal channels per vertical tunnel pattern set which are adapted tooverlay the five sets of tunnels 14₁ -1 . . . 14₁ -5. The horizontaltunnels 70 additionally include an outer contact pin 72 which isadapted, for example, to connect to a contact pin 74 of a peripheralcell, not shown. The horizontal width or length of the tunnels 70 are ofa predetermined dimension to accommodate a mutual overlay pattern of upto four vertical metal channels 76₁ , 76₂, 76₃ and 76₄. These fourchannels are adapted to be routed vertically through the adjacentvertical tunnel pattern 24₁ consisting of a set of six vertical tunnels78 having upper and lower contact pins 80 and 82 which are adapted to beconnected to the four vertical channels 76₁ . . . 76₄ as well as thecontact pins 72 and 68 of its immediately neighboring horizontal tunnel70 of tunnel pattern 22₂.

Thus, a unique single layer metallization pattern of both horizontal andvertical channels can be effected along with vertical or diagonal tunnelinterconnects in a roadbed layout which is repetitive and provides anarrangement which is optimized for an automatic layout program produced,for example, by a computer which determines a particular connection ofsignal routing for implementing a predetermined logic configuration. Theroadbed geometry shown in FIGS. 2 and 3 further provides a schemewhereby the internal cells 12 are sufficiently separated from thehorizontal and vertical wiring channels without fear of shorting orcutting off access to a particular cell by crossing over or under it.

In addition to the layout of the inner, outer and side peripheralroadbed areas, of particular importance is the layout of the basicinternal cells 12 which are repeated, for example, sixty-four (64) timesper cell row. Referring now to FIG. 4, each basic internal cell 12 islocated between five vertical tunnel contact pins, i.e the five contactpins 56hd 1, 56₂ . . . 56₅ of one set of tunnel patterns, for example,pattern 16₁ -3, as shown in FIG. 2, and five contact pins 54₁, 54₂ . . .54₅ of the vertical tunnel pattern 14₁ -1. The basic internal cellincludes four CMOS transistors consisting of two N-type transistors 84and 86 and two P-type transistors 88 and 90. In addition to the fourtransistors, a feedthrough tunnel 92 exists between the contact pins 56₁and 54₁ to provide a feedthrough capacility which allows signals to passunimpeded vertically through a particular cell row to another cell row.The P-type transistors 88 and 90 are formed by source and draindiffusions at the location of the +V power supply bus 28 while theN-type transistors 84 and 86 are formed by source and drain diffusionsat the location of the horizontal -V power supply bus 29. The gates G ofthe two transistors 84 and 86 are dedicated to the lower pins 54₃ and54₄ by way of polysilicon tunnel type members 85 and 87 while the gatesof transistors 88 and 90 are dedicated to the upper pins 54₃ and 54₄ byway of polysilicon tunnel type members 89 and 91 to provide a two inputdual entry into the cell. The remaining pins 54₂, 54₅ at the upper sideof the cell and the pins 56₂ and 56₅ at the lower side of the cell areuncommitted so as to provide two contact pins at the top and bottom ofthe cell for selective connection of the drains and sources of thetransistors 84, 86, 88 and 90. The two N-type transistors 84 and 86share a common intermediate source region S which includes a pair ofsource contacts 94 and 95. The drain regions D of the transistors 84 and86 include pairs of drain contacts 96, 97 and 98, 99. In a like manner,the common source region S' of the two P-type transistors include a pairof contacts 100 and 101 which lie intermediate two pairs of draincontacts 102, 103 and 104, 105 for the drain regions D'. In addition, upto three internal horizontal wiring channels 106, 107 and 108 areprovided as shown for making selective source and drain connections bymetallizations, not shown. With such a configuration, the cell 12 isvirtually symmetrical and is thus adapted for implementing a fourtransistor logic gate of any desired type having either a first orsecond vertical orientation with respect to the neighboring verticaltunnel patterns.

In order to illustrate a typical logic gate formed from the basicinternal cell layout shown in FIG. 4, reference is now made to FIG. 5which discloses the implementation of a dual input NAND gate which canbe accessed from either the top or bottom side of the cell 12. Inaddition to the underlying polysilicon tunnels 85, 87, 89 and 91 for thegates of transistors 84, 86, 88 and 90, whereby an input A can beapplied to either pin 54₃ or 56₃ while the other input B can be appliedeither at pin 54₄ or 56₄, the NAND gate as shown requires a verticalmetal channel connection 109 between the drain contacts 98 and 99, avertical metal channel connection 110 between the source contacts 100and 101, a horizontal and vertical metal channel connection 111 betweenthe drain contacts 97, 102 and 104, a horizontal and vertical metalchannel connection 112 spanning the polysilicon gate terminals 89 and 91between the drain contacts 103 and 105 as well as the contact pin 56₂and finally a vertical metal channel connection 113 between the draincontact 96 and the pin 54₂. All of the metal interconnections areadapted to be made at the same outermost level of the chip along withsignal routing interconnections being made at the same level in theroadbed area. This can be done by a single mask defining the variousconnections and laying down metallization in a manner well known tothose skilled in the art. Typically, this involves etching away of metalat all points at locations where metal is not wanted.

With respect to the peripheral cells that are used to interface theinternal cell configuration to external off-chip circuitry, not shown, atypical basic peripheral cell 18 is shown in layout form in FIG. 6A,whereas FIG. 6B is intended to illustrate the various semiconductordevices incorporated therein. Each basic peripheral cell 18 includesseven access contact pins 114₁ . . . 114₇, six of which connect totunnels 115₁ . . . 115₆ over which a power bus, for example, bus 30 isfound. The tunnels 115₁ . . . 115₆ terminate at internal contact pins116₁ . . . 116₆. A seventh internal contact pin 116₇ is shown connectedto a high impedance device 118 which includes a serpentine element 120coupled to the power bus 30 at the pad 121. On the other side of thecell, a second high impedance device 122 including the serpentineelement 124 is located over the power bus 38 and connects thereto viathe pad 125. Intermediate the power busses 30 and 38 diffusions are madeto implement a pair of gated diodes 126 and 128, two N-type transistors130 and 132 and two P-type transistor 134 and 136. On the other side ofthe power bus 38, there is located a bonding pad element 138 forproviding an off-chip connection as well as a spark gap protectivedevice 140. Also in the region of the bonding pad 138, there is locateda first resistor 142 and a second resistor 144 which spans the power bus38. Adjacent the bonding pad 138 is a protective spark gap 140.

FIG. 6B is schematically illustrative of these components in unconnectedform. The specific implementation of interconnection of the devices inthe peripheral cell 18, as shown in FIGS. 6A and 6B, follows the sameprinciples as those associated with the metal interconnects or channelsused to provide a specific logic gate configuration and therefore neednot be discussed further, inasmuch as a circuit designer will make aspecific implementation depending upon the specific needs of the user.Additionally, other special peripheral cells, the details of which arenot shown, may include other high impedance devices, low impedancedrivers, and special custom circuits as required in the specific circuitdesign.

Accordingly, what has been shown and described is a pattern ofpredefined unconvnitted active components and roadbed areas which permita selected logic application to be implemented at the outermostmetallization level and which is capable of being laid outautomatically, for example, by automatic layout programs contained in acomputer. To design a logic chip using this technique, the designerfunctionally defines the circuit to be generated in terms of logic cellsfrom a library of specially designed cells contained in the computermemory. Each cell consists of a metal interconnect pattern which, whensuperimposed in a proper position on the universal array shown anddescribed herein, will generate a mask for connecting the underlyingfixed devices and thus produce the desired logic function.

Having thus shown and described what is at present considered to be thepreferred embodiment of the invention, it should be noted that theforegoing has been made by way of illustration and not limitation andaccordingly all alterations, modifications and changes coming within thespirit and scope of the invention are herein meant to be included.

We claim:
 1. A universal array of active and passive circuit componentsformed on a semiconductor chip and adapted for single levelinterconnection to provide a desired circuit implementation, comprisingin combination:plural first direction rows of identical symmetricalinner cells of uncommitted circuit components; a bordering configurationof peripheral cells for providing an off-chip interface; a first roadbedarea on each side of said plural rows of inner cells, said first roadbedarea having a second direction tunnel pattern including at least threesets of plural parallel conductive tunnels mutually spaced apart in saidsecond direction for permitting first and second type interconnectionsbetween adjacent tunnel sets for second direction signal routing withinthe array and having respective predetermined conductive tunnel lengthspermitting plural parallel first direction conductive wiring channelscrossing thereover for first direction signal routing within the array;a second roadbed area at each end of said plural rows of inner cells aswell as said first roadbed area, said second roadbed area having a firstdirection tunnel pattern adjacent each first roadbed area and includinga set of plural parallel first direction conductive tunnels and havingrespective predetermined tunnel lengths permitting plural parallelsecond direction conductive wiring channels crossing thereover forsecond direction signal routing within the array, and a second directiontunnel pattern adjacent each row of inner cells and aligned with saidfirst direction tunnel pattern and including a set of plural parallelsecond direction conductive tunnels for selective connection of saidsecond direction conductive channels of said first direction tunnelpattern and having respective predetermined tunnel lengths permitting atleast one first direction conductive wiring channel crossing thereover;and a pair of peripheral power busses connecting opposite polaritypotentials to said plurality of inner and peripheral cells, said powerbusses running parallel and spaced across said peripheral cells aroundfour sides of said array and including a plurality of branch busses insaid first direction connected to respective power busses and crossingover said second direction tunnel pattern adjacent each row of innercells and running through said array for applying said opposite polaritypotentials to said plural first direction rows of inner cells, a pair ofbonding pads at one corner for connecting an external power source torespective said power busses, and a bridge over one power buss forconnecting the other power buss to one bonding pad while maintainingseparation from the one buss and the other bonding pad, said peripheralcells each including a plurality of tunnels crossing under one saidpower buss and providing connections between said peripheral cells andinner cells, a further bonding pad for connection to external circuitmeans, and a pair of high impedance devices connected between said powerbusses and said peripheral cells.
 2. The universal array as defined byclaim 1 wherein said first direction comprises the horizontal directionand said second direction comprises the vertical direction.
 3. Theuniversal array as defined by claim 1 wherein said first roadbed areabetween rows of cells consists of a tunnel pattern including five setsof second direction tunnels.
 4. The universal array as defined by claim3 wherein the second direction spacing between said five sets ofconductive tunnels is substantially equal.
 5. The universal array asdefined by claim 4 wherein second direction spacing is less than therespective predetermined tunnel lengths.
 6. The universal array asdefined by claim 5 wherein the respective tunnel lengths of said fivesets of conductive tunnels are substantially equal.
 7. The universalarray as defined by claim 6 wherein the widths of the individual tunnelsof said five sets of tunnels are substantially equal and less than theirrespective lengths.
 8. The universal array as defined by claim 6 whereinthe lengths of said conductive tunnels of said second direction patternof said second roadbed area are substantially equal to the tunnellengths of said five sets of conductive
 9. The universal array asdefined by claim 8 wherein the widths of the conductive tunnels of saidfirst direction tunnel pattern of said second roadbed area are greaterthan the widths of the conductive tunnels of said second directiontunnel pattern of said second roadbed area.
 10. The universal array asdefined by claim 1 wherein each cell of said plural rows of cellslaterally spans an equal number of second direction conductive tunnelsof one of said at least three sets of tunnels of said first roadbed areaon opposite sides of said cell.
 11. The universal array as defined byclaim 10 wherein each of said equal number of second directionconductive tunnels terminates in a respective pair of conductive contactpads or pins, one of which is located adjacent said cell and one ofwhich is located a tunnel length away from said cell.
 12. The universalarray as defined by claim 11 wherein each cell includes a feedthroughconductive tunnel connected to one adjacent contact pad on oppositesides of said cell.
 13. The universal array as defined by claim 11wherein each cell comprises a plurality of active semiconductor devicesfor implementing a logic gate, said devices respectively having an inputterminal coupled to individual contact pads of said adjacent contactpads.
 14. The universal array as defined by claim 13 wherein each saidcell includes four semiconductor devices two of which are located onrespective opposite halves of said cell and wherein said four deviceshave respective input terminals coupled to two individual contact padson opposite sides of said cell.
 15. The universal array as defined byclaim 14 wherein said semiconductor devices comprise transistors. 16.The universal array as defined by claim 15 wherein said two transistorson opposite halves of said cell are respectively of oppositesemiconductivity type.
 17. The universal array as defined by claim 15wherein two of said transistors comprise N-type transistors and two ofsaid transistors comprise P-type transistors.
 18. The universal array asdefined by claim 15 wherein said transistors include gate, drain andsource diffusion regions and wherein said gate regions are common tosaid input terminals.
 19. The universal array as defined by claim 14wherein said equal number of second direction conductive tunnelscomprise five conductive tunnels on opposite sides of said cell andwherein said respective input terminals are coupled via respectivepolysilicon tunnels to two individual contact pads of said five tunnelson opposite sides of said cell and wherein said cell additionallyincludes a polysilicon feedthrough conductive tunnel connected atopposite ends to another contact pad of said five tunnels on oppositesides of said cell.
 20. The universal array as defined by claim 19wherein said semiconductor devices comprise three terminal devices oneof which comprises said input terminal and wherein the two remainingterminals are adapted to be selectively coupled via metals interconnectsto the remaining contact pads of said five conductive tunnels onopposite sides of said cell.